The present invention relates to the electrical connection of integrated circuits to printed circuit boards, and in particular, to methods and apparatus for interconnecting a ball grid array of an integrated circuit to matching pads of a printed circuit board.
It is a challenging process to interconnect chip packages containing VLSI (very large scale integrated) circuits having large I/O pin counts to an underlying printed circuit board (PCB). Conventional interconnection techniques include pin grid arrays (PGAs) and ball grid arrays (BGAs). BGAs may accommodate more connections in a miniature package. They also cause less distortion of signals, at least partly because they have lower thermal resistances. Many such chip packages employ ball grid arrays (BGAs) to achieve VLSI-to-PCB interconnections. Among the problems with interconnecting ball grid arrays to a PCB include excessive resistance and inductance of the interconnection material as well as differences in thermal expansion and other mechanical stress related issues.
Reference is now made to FIGS. 1-2, which illustrate prior art techniques of coupling a VLSI circuit 10 to a PCB 20 using a BGA. There are two conventional methods for interconnecting the balls pads 12 of the ball grid array to the aligned contact pads 14 of the printed circuit board 20. As shown in FIG. 1, one technique employs solder 16 to couple the ball pads 12 to the contact pads. Assuming that the ball pads 12 are made of solder, such ball pads 12 are partly melted and then cooled and solidified to form an electrical connection. However, the soldering process is complex and costly. Moreover, any bending and/or thermal expansion of the PCB 20 is transmitted directly to the VLSI circuit package 10. This may cause the solder joints 14 to fracture due to thermal and/or mechanical stress. The thermal stress may result from a difference in the coefficient of thermal expansion between the solder 16, the contact pads 14 (which may be formed from gold or copper), and the materials forming the PCB 20 and/or the chip package 10.
As shown in FIG. 2, the other technique employs coil springs 18 to interconnect the ball pads 12 to the contact pads 14. The coil springs 18 are sandwiched between the ball pads 12 and the contact pads 14, thereby compressing the springs 18. A clamping system 22 couples the chip package 10 to the PCB 20 such that the ball pads 12, the coil springs 18, and the contact pads 14 are in registration. The springs 18 are in compression and bias against the ball pads 12 and the contact pads 14, thereby establishing the electrical interconnection. Compared to the soldering method, the coil springs 18 may be easier and cheaper to implement. They may also be less susceptible to thermal and/or mechanical stress. However, each coil spring 18 has considerable electrical resistance (which is proportional to its length and inversely proportional to its cross-section area). Further, each coil spring 18 exhibits undesirable electrical resistance inductance (which is proportional to the number of turns thereof). Still further, each coil spring 18 exhibits undesirable electrical capacitance (formed between adjacent turns of the spring). The resistance, inductance and capacitance introduced by the coil springs 18 may significantly and undesirably affect the signal response through the interconnection, particularly at high frequencies.
Therefore, there is a need in the art for an new interconnection solution to couple a ball grid array of an integrated circuit to a matching matrix of pads on a printed circuit board, which has improved electrical characteristics and a better mechanical performance.